1. Field of the Invention
This invention relates generally to computing systems, and, more particularly, to a system and method for delaying power-up of a power supply.
2. Description of the Related Art
Turning now to FIG. 1A, a computer system 100A is powered by a 110V, 60 Hz alternating current (AC) delivered through an electrical outlet 115 via a power plug 110 and a power cord 105. The computer system 100A may be a typical desktop computer configured to run one of the x86 operating systems. A computer system 100B of FIG. 1B is powered from a battery 120, typically 12V direct current (DC). The computer system 100B may also accept a power cord 105, similar to the computer system 100A, to supply electrical power, when there is an electrical outlet 115 available.
Turning now to FIG. 2, a portion of the internal components of the computer system 100A is shown. Electrical power is provided through the power cord 105 to a power supply 210 to provide electrical power to the computer system 100A. The power supply 210 converts the provided AC electrical power to the DC voltages and amperages necessary for powering the computer system 100. Electrical and control signals are provided from the power supply 210 to power planes (not shown) in a motherboard 205 (also called a main board or back plane) through a plurality of wires 215 connected to a plurality of pins (e.g. FIG. 3) in an electrical connector 220A, which mates with a corresponding electrical connector 220B on the surface of the motherboard 205. Illustrative components on the motherboard 205 include one or more integrated circuits 230 and one or more cards 240, which may mate to the motherboard 205 through a connector 245. Examples of integrated circuits 230 include processors, cache memory chips, chip sets (e.g. north bridges and south bridges), controller chips, etc. Examples of cards 240 include those that conform to the Industry Standard Architecture (ISA), Extended Industry Standard Architecture (EISA), Peripheral Component Interconnect (PCI), etc. bus definitions. Main memory, in the form of random access memory (DRAM, SDRAM, RDRAM, etc.), may also be connected to the motherboard 205 through the cards 240.
FIG. 3 shows the various signals carried in one embodiment of the power connector 220A, a 20-pin ATX power connector. Pins 1, 2, and 11 are 3.3V. Pins 4, 6, 19, and 20 are +5V, while pin 18 is xe2x88x925V. Pin 9 is 5VSB (stand-by), a +5 V power signal that is always on when the power supply is energized, even while the other power lines (pins 1, 2, 4, 6, 10-12, and 18-20) are off. Pin 10 is +12V, while pin 12 is xe2x88x9212V. Pins 3, 5, 7, 13, 15, 16, and 17 are ground (also referred to as common). Two signal pins provide signaling. Pin 8 is for a power-OK signal. Pin 14 is a power supply-on (PS-ON#) pin that signals the power supply 210 to provide power when the PS-ON# pin is made active low.
Turning now to FIG. 4, an exemplary computer system layout 400, is shown. The computer system 400 includes a processor 402, a north bridge 404, main memory 406, Advanced Graphics Port (AGP) memory 408, a PCI bus 410, a south bridge 412, a back-up battery 413, an AT Attachment (ATA) interface 414 (more commonly known as an Integrated Drive Electronics (IDE) interface), a universal serial bus (USB) interface 416, a Low Pin Count (LPC) bus 418, an input/output controller chip (SuperI/O(trademark)) 420A, and BIOS memory 422. It is noted that the north bridge 404 and the south bridge 412 may include only a single chip or a plurality of chips, leading to the collective term xe2x80x9cchipset.xe2x80x9d It is also noted that other buses, devices, and/or subsystems may be included in the computer system 400 as desired, e.g. caches, modems, parallel or serial interfaces, SCSI interfaces, network interface cards, etc. [xe2x80x9cSuperI/Oxe2x80x9d is a trademark of National Semiconductor Corporation of Santa Clara, Calif.]
The south bridge 412, as shown, includes a power control module 415. The power control module 415 is configured to provide electrical and battery power control and regulation functions for the computer system 400. The power control module 415 may operate according to the Advanced Configuration and Power Interface Specification (ACPI Specification). Revision 1.0b of Feb. 2, 1999 of the ACPI Specification is hereby incorporated by reference in its entirety. An alternative embodiment of the SuperI/O(trademark) chip 420B may include the power control module 415, instead of the south bridge 412. The power control module 415 may also be divided between the south bridge 412 and the Super I/O(trademark) chip 420B, as desired.
The processor 402 is coupled to the north bridge 404. The north bridge 404 provides an interface between the processor 402, the main memory 406, the AGP memory 408, and the PCI bus 410. The south bridge 412 provides an interface between the PCI bus 410 and the peripherals, devices, and subsystems coupled to the IDE interface 414, the USB interface 416, and the LPC bus 418. The Super I/O(trademark) chip 420A is coupled to the LPC bus 418.
The north bridge 404 provides communications access between and/or among the processor 402, the main memory 406, the AGP memory 408, devices coupled to the PCI bus 410, and devices and subsystems coupled to the south bridge 412. Typically, removable peripheral devices (e.g. cards) are inserted into PCI xe2x80x9cslotsxe2x80x9d (not shown) that connect to the PCI bus 410 to couple to the computer system 400. Alternatively, devices located on a motherboard may be directly connected to the PCI bus 410.
The south bridge 412 provides an interface between the PCI bus 410 and various devices and subsystems, such as a modem, a printer, keyboard, mouse, etc., which are generally coupled to the computer system 400 through the LPC bus 418 (or its predecessors, such as an X-bus or the ISA bus). The south bridge 412 includes the logic used to interface the devices to the rest of computer system 400 through the IDE interface 414, the USB, interface 416, and the LPC bus 418.
Devices that couple to the USB or ATA interfaces may also be powered through the power planes of the motherboard 205. Secondary power supply connectors (not shown) often connect directly to hard drives or CD ROM drives that transmit data through the ATA interface. USB devices may be powered through the USB interface or through an external power supply.
During testing of computer systems, such as the computer system 100A, it is common to unplug the power connector 220A from the power connector 220B on the motherboard 205 before swapping out integrated circuits 230 or cards 240. Unplugging the power connector 220A removes electrical power from the computer system 100A and allows for removal and insertion of components that use electrical power from the computer system 100A with less likelihood that they will be damaged by stray voltages, or inadvertent or intermittent electrical connections. It is noted that semiconductor devices, such as integrated circuits 230, are prone to electrical damage (e.g. punch-through or lockup) from stray electrical signals, even from static electricity.
Turning to FIG. 5A, the proper orientation of the power connector 220A to the power connector 220B during insertion is shown. The plurality of wires 215 is shown connected to the power connector 220A. The connector 220B is shown below the power connector 220A, ready to accept and mate with power connector 220A. Note that the plane of incidence 510A of the power connector 220A is parallel to the plane of incidence 510B of the power connector 220B. Upon contact, where the plane of incidence 510A coincides with the plane of incidence 510B, the angle of incidence is substantially zero degrees. When the power connector 220A is inserted into the power connector 220B as shown here in FIG. 5A, the 5V standby pin energizes. Upon receiving a feedback load signal, the remaining power planes energize in the proper order, first 3.3V, 12V, and then 5V.
In FIG. 5B, a more typical orientation of the power connector 220A relative to the power connector 220B during insertion is shown. Note that the angle of incidence between the plane of incidence 510A of the power connector 220A and the plane of incidence 510B of the power connector 220B is now greater than zero. When the power connector 220A is inserted into the power connector 220B as shown here in FIG. 5A, it has been determined that the power planes may energize in improper order, possibly leading to damaged integrated circuits 230 or cards 240.
A similar insertion orientation that may also lead to problems is rocking the connector 220A back and forth from the position shown in FIG. 5B to its mirror image. The angle of incidence between the planes 520A and 520B minimizes until the power connectors 220A and 220B are connected. Rocking the power connector 220A as it is inserted into the power connector 220B may also energize the power planes in improper order, possibly leading to damaged integrated circuits 230 or cards 240.
In one aspect of the present invention, a method is provided for providing power to a computer system. The method includes providing a standby signal. The method further includes receiving a power up signal. The method also includes delaying the power up signal. The method further includes passing the power up signal to the computer system after delaying the power up signal.
In another aspect of the present invention, a system is provided. The system includes a detection circuit and a delay circuit. The detection circuit is configured to receive a standby signal from a power supply. The detection circuit is also configured to output a control signal. The delay circuit is coupled to receive the control signal. The delay circuit is configured to output a delayed control signal for the power supply in response to the control signal after a predetermined period of time.